With the obvious similarity of the proposed test generation methods used at the logic level and the register transfer level, it is a bit confusing to see the duplication of definitions of such terms as gate fan-in, fan-out, and transitive fan-out in S ection 3.1. Similarly, on page 26, the authors do not clearly explain why the machine shown in Figure 2.6 has an initialization problem.Ī different example of obscurity is on page 107, where a few techniques are recommended equally, mixed with references to other sources, without any discussion of their advantages and disadvantages. (The abbreviation STG, which is used throughout the book for these graphs, seems like a poor choice, since “STG” has traditionally been used to refer to signal transition graphs, a class of interpreted Petri nets.) For instance, on page 21, some terms are used that are not formally defined, such as concatenation of state graphs, product state graph, and exclusive-or of two state graphs. The examples of circuits, their state transition graphs, and the application of the algorithms for them often help to build some intuition, but this is far from being a sense of confidence. To this end, the book is at least helpful as a pointer to the right source. In each of these domains, however, readers without a good background would hardly be able to understand the details without referring to a more substantial text. The book also presents binary decision diagrams and traversal techniques based on recursive range computation and transition relations. Finite state machine graph traversal and enumeration techniques are presented. They introduce sequential test generation (the crucial points being “excitation state,” “state justification,” and “state differentiation”) and test generation approaches (random and deterministic approaches, iterative array-based approaches, and forward and reverse time processing). The authors define synthesis for testability, design verification, implementation verification, logic verification, and so on. At the same time, it provides some introductory material on the relevant terminology.
#SEQUENTIAL TESTING AT INTEL VERIFICATION#
The book, with its obvious orientation toward the needs of the advanced reader, provides an insightful treatment of recent progress in test generation and verification methods for synchronous, sequential logic circuits.
The trouble, however, as is common in disciplines that rely heavily on optimization, is that it is extremely hard to identify which techniques would be most suitable, as most of the problems are computationally hard and require flexible heuristics. It is fairly systematic, however, and has a good chance to become a text when most of the ample references to recent and prominent papers are replaced by a reasonable amount of material outlining the best approaches and algorithms available in this area. Both its size and its content show that it is a research monograph. Unfortunately, this book does not improve this situation radically.
#SEQUENTIAL TESTING AT INTEL SOFTWARE#
dissertations, not in industrial CAD software or undergraduate project work.
Most of today's methods are still found only in research lab prototype tools and Ph.D.
Furthermore, it is rare for a book to attempt to cover the formal verification of sequential circuits. Testing sequential circuits and synthesis of these circuits for testability (other than using scan-based techniques, which have an associated area or performance penalty) are much more difficult. Similarly, a number of existing techniques and tools can efficiently synthesize and generate tests for such circuits. Quite a few good texts about combinatorial logic testing are available.
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